The report, covered on August 16 by Tom's Hardware and Firstpost, lands amid an intensifying race to redesign AI infrastructure for reasoning models and autonomous agents — a shift we have been tracking in our breaking AI news coverage. According to SemiAnalysis, Google and its customers are pushing for TPUs with on-package CPU cores for reinforcement learning (RL) and potentially other CPU-heavy workloads, and AMD is a strong candidate to supply the missing pieces.
Why Google Would Not Need AMD to Design a TPU
The analysts pour cold water on the simplest reading of the story. Google already has substantial in-house expertise in accelerator architecture, honed over eight TPU generations, and would not necessarily need AMD to design another conventional TPU. The chances of AMD implementing Google's next inference chip (TPU V10i) or training chip (TPU V10t) are considered low.
Instead, the analysts believe Google may need things a CPU maker like AMD can provide: CPU intellectual property, programmable logic, interconnects, or advanced packaging expertise. In other words, the story is less about AMD building Google's AI accelerator and more about what a hybrid chip — Google's tensor compute married to AMD's general-purpose cores — could unlock.
Reinforcement Learning Is Turning AI Silicon Inside-Out
The driver is a genuine shift in how AI systems consume compute. Conventional large language model training remains overwhelmingly accelerator-heavy: matrix math, all day, on GPUs and TPUs. But reinforcement learning for reasoning and agentic models is different. RL pipelines interleave accelerator operations with large amounts of scalar, branchy, general-purpose computation — environment simulation, reward computation, orchestration of many parallel rollouts — which runs far better on CPUs.
Google's own system designs already reflect that shift. According to the report, Google's inference-focused TPU 8i systems — built for inference, reasoning, and RL workloads — provision one Google Axion CPU for every two TPUs. By comparison, servers based on the seventh-generation TPU used one Intel Xeon "Emerald Rapids" processor for every four TPUs. Doubling the CPU-to-accelerator ratio is a strong signal of where Google sees workloads heading, and packaging CPU cores directly alongside the accelerator is the logical next step: shorter data paths, less data movement, and better power efficiency for exactly the workloads that agentic AI demands.
The MI300A Precedent
AMD brings directly relevant experience to such a project. Its Instinct MI300A — deployed in elite-class supercomputers — was the first true APUs at data-center scale, combining x86 Zen CPU chiplets and GPU compute chiplets with shared memory in a single package. A future Google design could take a similar shape: Google's TPU compute chiplets paired with AMD CPU technology and high-bandwidth memory, with AMD potentially handling parts of the packaging and integration.
Both companies have reason to talk. For Google, the move would extend a silicon strategy that already spans multiple partners — its eighth-generation TPU lineup, announced in April 2026, split into dedicated training (8t) and inference (8i) chips, and reporting earlier this year described Google assembling a multi-partner custom-silicon supply chain spanning Broadcom, MediaTek, and Marvell to challenge Nvidia in inference. For AMD, a Google design win would be a marquee endorsement of its chiplet and packaging technology — and a foothold in custom AI silicon, a market where Nvidia's dominance remains largely unchallenged.
Important Caveats
SemiAnalysis itself stresses that significant uncertainty remains. The exact nature of AMD's reported involvement is unclear, the partnership has not been confirmed by either company, and the analysts frame their reasoning as informed speculation about why such a collaboration would make sense rather than a confirmed product roadmap.
But the deeper signal matters more than the deal itself. If the reports are accurate, the most significant development is not Google and AMD working together — it is Google exploring CPU-heavy TPU variants designed specifically for reinforcement learning, reasoning, and agentic AI. The industry spent a decade optimizing chips for one giant matrix multiplication. The next generation of AI hardware is being shaped by workloads that look much less like a single mind thinking and much more like thousands of agents exploring, failing, and learning at once.
What to Watch
For the broader industry, three things would turn this report from speculation into a trend. First, any sign of custom-silicon deals that pair accelerator and CPU vendors rather than pitting them against each other — the same logic that pushed AMD into the MI300A and Nvidia toward Grace-Hopper-style integrated systems now appears to be shaping hyperscaler ASIC roadmaps. Second, whether Google's TPU 8i deployment ratios continue drifting toward more CPU per accelerator, which would independently confirm the RL workload thesis. Third, AMD's own earnings commentary: a custom design win at Google's scale would be material enough to surface in financial disclosures eventually.
Neither Google nor AMD has commented on the report, and SemiAnalysis notes its analysis is based on the strategic logic of the pairing rather than confirmed contracts. But in a year in which Google has already split its TPU line into training and inference products, signed multi-partner silicon supply deals, and hoarded CPU capacity around its newest accelerators, a CPU-heavy TPU variant is less a surprise than the next logical move.
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