Google has expanded its eighth-generation TPU lineup with two new specialized systems: TPU 8i Max, which combines two inference chips on a single package for long-context agentic workloads, and TPU 8tx, built for confidential, hardware-isolated inference aimed at regulated enterprises and governments. Tom's Hardware reported the additions on Thursday.
The move rounds out a family that Google began in April with the TPU 8t, designed for large-scale AI training, and the TPU 8i, built for general-purpose inference work such as sampling, serving and reasoning. With the new variants, the eighth-generation lineup now covers training, standard inference, secure inference and maximum-bandwidth agentic inference — a matrix of options that reflects how differently enterprises now use AI hardware. This chip news is part of our latest AI developments coverage across the AI hardware market.
What the new chips do
TPU 8i Max puts two 8i chips on one package, doubling the compute, SRAM and high-bandwidth memory bandwidth of the original 8i. The design targets long-context agentic work — scenarios in which AI agents carry very large working contexts across multi-step tasks.
Tom's Hardware framed the bandwidth doubling as a way around what Google calls the memory wall, the bandwidth bottleneck that becomes acute "when dozens of AI agents work together across an entire software codebase." Larger context windows — with larger models targeting around 1 million tokens — mean larger KV caches, partly held in SRAM, and each new token generated must read that cache back from memory. Doubling HBM bandwidth in a single package attacks precisely that bottleneck, and the publication noted it is a different route from Nvidia's approach of pairing a second chip type for decoding with a storage tier for context.
TPU 8tx, meanwhile, is built on the same silicon as the previously announced training-oriented 8t, but is configured for confidential computing: hardware-isolated inference for regulated enterprises and governments that need proof their data and models are protected during processing. The system swaps the Arm-based Axion host CPUs used by the 8t and 8i for a 5th Gen AMD EPYC processor and adopts Google's Boardfly networking.
Notably, Google has yet to share detailed specifications, prices or ship dates for either new system, so buyers currently have renderings and positioning rather than orderable products.
Renderings Google published alongside the announcement show a TPU 8tx board carrying four chips, alongside four TPU 8i Max boards, each carrying two chips on a single package — a physical illustration of how far the eighth-generation family has diverged from the one-chip-fits-all accelerator model of earlier generations.
TPU Sync: the software layer for agent memory
Alongside the silicon, Google is leaning on software to solve the agent-memory problem. TPU Sync is an open-source "model-state layer for TPU clusters" that automatically tiers massive KV caches off the chip in milliseconds, moving them down to host DRAM and, experimentally, shared storage.
According to Google, this can cut KV-cache transfer latency by more than 90%, with corresponding gains in time-to-first-token — the delay a user experiences before an AI system starts responding. For agentic workloads, where a single session may involve dozens of sequential model calls that each need access to the same accumulated context, cache management is becoming as important as raw compute.
Why it matters for the AI hardware market
TPUs have become a fast-growing business for Google, which claims nearly 100 customers for the chips — including Meta, whose adoption of Google TPUs in its data centers marked one of the most significant competitive incursions into Nvidia's territory. The more modular approach Google is taking with the eighth-generation family, the company says, allows it to deliver specialized systems "in a matter of months rather than years," helping that customer growth along.
The timing of the announcement is striking. Google's chip expansion landed on the same day Nvidia announced that CEO Jensen Huang has resigned, with CFO Colette Kress appointed interim CEO — an extraordinary leadership disruption at the very company whose GPUs dominate the market Google's TPUs are chipping away at. The two events are unrelated in cause, but together they underline how competitive and how volatile the AI infrastructure market has become.
For enterprises evaluating AI infrastructure, the additions signal that the choice set is widening: training-optimized silicon, general inference, secure inference for regulated data, and maximum-bandwidth packages for agent fleets are becoming distinct product categories rather than one-size-fits-all accelerators. When Google publishes pricing and availability details, the practical question for buyers will be whether the 8i Max's doubled bandwidth translates into enough throughput for agentic fleets to justify a premium over standard 8i deployments.
The modularity also has a supply-side logic. Rather than waiting years for a next-generation design to cycle through the full hardware stack, Google can recombine existing silicon — as it did by moving 8t silicon into a secure-inference package with a different host CPU — to reach niche segments faster, while keeping a common software stack across all variants. That speed is itself a competitive weapon in a market where customer requirements are shifting quarterly.
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